Description: 至简设计法--VGA显示矩形
工程说明
本工程VGA显示要求：在显示屏边缘上显示一个红色边框（边框宽为20像素），在屏幕的中央显示一个绿色矩形（矩形长为150像素，高为100像素）。
案例补充说明
本设计的VGA图像显示是基于FPGA实现的，采用了Verilog HDL语言编写，再加上有明德扬的至简设计法作为技术支撑，可使程序代码简洁且执行效率高。(the minimalist design, --VGA shows rectangles
Engineering description
This project VGA display requirements: display a red border (border width of 20 pixels) on the edge of the display, in the center of the screen shows a green rectangle (rectangle is 150 pixels, 100 pixels high).
Case Supplement
The design of VGA image display is realized based on FPGA, using Verilog HDL language, plus Ming Stankovic to simple design method as technical support, can make the code simple and high efficiency.) Platform: |
Size: 324608 |
Author:明德扬科教
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Description: Mentor公司的ModelSim是业界最优秀的HDL语言仿真软件，它能提供友好的仿真环境，是业界唯一的单内核支持VHDL和Verilog混合仿真的仿真器。它采用直接优化的编译技术、Tcl/Tk技术、和单一内核仿真技术，编译仿真速度快，编译的代码与平台无关，便于保护IP核，个性化的图形界面和用户接口，为用户加快调错提供强有力的手段，是FPGA/ASIC设计的首选仿真软件。(Mentor's ModelSim, the industry's best HDL language simulation software, offers a friendly simulation environment and is the industry's only single-core simulator supporting VHDL and Verilog mixed simulations. It uses direct optimization of the compiler technology, Tcl / Tk technology, and a single kernel simulation technology, compile and emulate fast, compiled code has nothing to do with the platform, easy to protect IP core, personalized graphical interface and user interface to speed up the user to debug wrong Provide a powerful means of choice for FPGA / ASIC design simulation software.) Platform: |
Size: 523264 |
Author:冰激凌很牛
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Description: 题目1：设计一个8位数字显示的简易频率计。要求：
①能够测试10Hz~10MHz方波信号；
②电路输入的基准时钟为1Hz，要求测量值以8421BCD码形式输出；
③系统有复位键；
④采用分层次分模块的方法，用Verilog HDL进行设计。
⑤写出测试仿真程序(Topic 1: Design a simple frequency meter with 8 digits display. Requirement:
It can test 10 Hz ~ 10 MHz square wave signal.
(2) The reference clock input by the circuit is 1Hz, which requires the measured value to be output in the form of 8421BCD code.
(3) The system has reset keys;
(4) The design is based on Verilog HDL with the method of hierarchical module.
Write out the test simulation program) Platform: |
Size: 140288 |
Author:鹏jjjjj |
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